1. Field of the Invention
The present invention relates to debugging of processing computer systems which include an internal cache wherein not all microprocessor instructions and data can be monitored outside of the microprocessor.
2. Description of the Related Art
Software for information processing devices has become increasingly more complex. Thus, more sophisticated tools are necessary to aid in debugging problems typically encountered when implementing such software. One powerful tool which has been developed is the in-circuit emulator (ICE) which monitors the instruction and data stream into and out of a microprocessor. Typically, an ICE comprises a logic analyzer together with memory which records a data or instruction stream over a predetermined window of time through a data communication channel such as a system bus.
In a typical information processing system, one or more central processing unit (CPU) modules communicate with memory or input/output (I/O) units via a system bus. A typical CPU module includes a CPU having an internal cache memory which communicates with an external cache memory via a bidirectional communications bus. The external cache memory typically communicates with the system bus via a local data bus, a local address bus, and a local control bus.
As is well known in the art, a cache memory is a fast memory storage unit which is under the control of the CPU within each of the CPU modules. A cache memory may be either a write-through cache memory or a write-back (sometimes called copy back) cache memory.
A write-through cache memory always immediately writes data changes within memory locations of the cache to corresponding memory locations within the main memory module. Thus, for example, if the central processing unit within the first CPU module writes new data into the cache memory within the first CPU module at a given address, the cache memory will immediately write the same data into the corresponding address in the main memory module via the multiprocessor bus. It should be noted here that the main memory module will typically have a portion of memory which has a mapped one-to-one correspondence to memory locations within the cache memories of each of the CPU modules. The memory locations within the main memory module that can have corresponding cache memory locations are typically called cacheable memory addresses. At any time, a portion of the cacheable memory addresses are mapped into the cache memories. The mapped portions typically change over time as the CPU modules request data from different portions of the main memory. When changes occur, the data in the cache memories are swapped out and replaced with data from the main memory. It is important that the corresponding memory locations within each of the cache memories and the main memory unit contain the same data because when an input/output device wishes to access a memory location, the memory location will typically be accessed within the main memory unit. However, if the main memory unit does not have the same data as the cache memory of a corresponding address, this indicates that the main memory unit has yet to be updated with the most recent data which is present within the address sought by the input/output device. Thus, erroneous data may be retrieved by the input/output device if the main memory unit does not have the same data as the corresponding cache memory address.
Although write-through cache memories guarantee that corresponding memory locations within the cache memories and the main memory module have the same data, the necessity of immediately accessing the multiprocessor bus each time the CPU within a CPU module writes to the cache memory causes a number of interruptions on the multiprocessor bus. These interruptions often create bus inefficiencies which may severely compromise the performance of the overall multiprocessor system.
To overcome the difficulties associated with write-through cache memories, write-back cache memories have been used. Write-back cache memories write data from the cache memory to a corresponding memory location within the main memory unit at a later time when the data is requested by another device (such as an input/output device or another CPU module). This increases the overall efficiency of the system since the CPU may update data several times within a write-back cache location without writing these updates out to the main memory. Thus, the system bus typically is used less frequently in write-back cache memory systems. Furthermore, the internal cache memory within a CPU may also be write-back so that several data and instruction modifications may be made solely within the CPU before the final product is written out to the external cache memory.
In order to monitor the operation of the CPU for debugging purposes, an ICE may be connected along a data/instruction path such as a system bus, the local data address and control bus from the external cache memory to the system bus, or the bidirectional communication bus between the external cache memory and the CPU. When monitoring the operation of the CPU, the ICE is programmed to recognize a prespecified data sequence. For example, the ICE may be programmed to trigger when a particular data sequence is written to a specified memory address location, or when several data sequences are written in succession to specified memory address locations. As soon as the ICE detects the prespecified data sequence at the given address location or locations, the ICE outputs a record of the entire data and instruction sequence which occurs proximate in time to the specified data sequence which triggered the ICE. In some applications, the ICE will output a record of the data and instruction sequence which follows the specified trigger data sequence within some time window, while in other applications the ICE will output a record of the entire data and instruction sequence which preceded the prespecified data sequence by some time window. In yet other applications, the ICE outputs a record of the data and instruction sequence both before and after the pre-specified trigger data sequence.
The data record output by the ICE can be used for debugging purposes and is therefore highly useful in design and testing of new software applications. A significant difficulty is encountered, however, in systems which incorporate a write-back internal cache so that not all of the microprocessor instructions and data are visible outside of the microprocessor where they can be monitored by the ICE. Data writes to the internal cache of the microprocessor, and data reads from the internal cache of the microprocessor, are essentially invisible because many of the reads and writes are never output to the external cache or to the system bus where these data transfers and instruction signals can be monitored by the ICE. Thus, in microprocessor systems which include an internal cache memory, it becomes very difficult to analyze and debug complex new software.
In order to monitor the instruction and data stream into and out of the internal cache of a microprocessor, some systems simply disable the entire cache memory so that all instruction and data transfers are carried out over the system bus. However, in such implementations, a microprocessor system is typically slowed down considerably, and errors which would normally be produced within a high speed system are often not reproducible when the microprocessor has been slowed down by the disabling of all cache memories.
Other systems have contemplated disabling only the internal cache within the microprocessor. The ICE can then be interposed between the microprocessor and the external cache to monitor all operations executed by the microprocessor. While this does slow down the overall microprocessor system considerably, this effect is somewhat minimized by the fact that the external cache is operable. However, unless the external cache has been designed to allow for a condition wherein the internal cache is disabled, such disabling may constitute an illegal state for the external cache. That is, the external cache memory may not be equipped to handle communications with the microprocessor when the internal cache within the microprocessor is disabled. In such cases, the external cache may, for example, transmit an entire cache line to the microprocessor when the microprocessor only expects a single data block since it is in the cache disable mode. In such instances, the performance of the microprocessor system may be severely compromised.
A third approach is to use a special "bond-out" microprocessor in the ICE. Such chips include special output terminals which may be used to monitor the operation of the internal cache memory within a microprocessor. This bond-out allows the ICE access to some internal signal lines that may enable more accurate monitoring of the system. However, such chips are quite expensive and generally not available for all microprocessor types.
A fourth approach is to have the operating system map different areas of memory as non-cacheable. However, with this approach, the resolution of the memory management unit (MMU) in the microprocessor is such that it would generally require an entire page of memory for the operating system to map different areas of memory as non-cacheable. For example, for an 80486, an entire 4 kilobyte page of memory would be required for the operating system to map these areas of memory as non-cacheable. Also, such memory mapping requires intimate knowledge of the operating system kernel and access to the source code.
Finally, several microprocessors have internal registers that can be used for debugging. Such registers allow the debugging engineer to specify an event which will cause the microprocessor to take a "debug" exception. That is, the microprocessor would trigger when, for example, a specified address and/or data pattern is observed. However, since the internal registers within the microprocessor are generally small, this technique often allows monitoring of only one to six addresses or break (i.e., trigger) points. Therefore, more complex patterns which might be required to properly debug a complex software program would not be observable using such devices. Additionally, since none of the activity is visible by the ICE, a debugging engineer is often left to guess which section of code actually caused the trigger. Furthermore, the specified events which trigger the break points are typically simple and do not allow for more complicated trigger options that are typically necessary for complex software implementations and are typically available with an external logic analyzer.